The VHDL Standard.

1 INTRODUCTION
This report is intended to give an overview of the current status of the VHDL IEEE
Standard 1076. The objective of this document is not to provide an overview of VHDL. The
objective is to help positioning the existing VHDL standards as well as the ongoing
standardization activities. The report also highlights important European VHDL activities.
Chapter 1 is this introduction.
Chapter 2 lists existing standards and standardization activities. For each activity, it
highlights the objectives, current status and future plans.
Quite some organizations are working on VHDL standardization or other VHDL
promoting activities. To help understand the positioning and the goals of these
organizations, Chapter 3 contains a list of these organizations.
Chapter 4 provides some details on European VHDL related tool efforts.
Chapter 5 gives a few examples of European companies using VHDL. The chapter also
lists European R&D programmes related to VHDL.
Chapter 6 lists some conclusions.
All practical information available has been gathered into Chapter 7. This includes
electronic repositories (which ones and how to access them) and an extensive list of
contacts within companies and organizations, plus various other information.

2 STATUS OF THE VHDL STANDARD
2.1 VHDL IEEE Std 1076-1987
The VHDL language was an offshoot of the VHSIC (Very High-Speed IC) program, funded
by the U.S. Department of Defense (DoD), and was first proposed in 1981. The
development of VHDL was carried out by IBM, Texas Instruments, and Intermetrics,
starting two years later in 1983. In August 1985, version 7.2 of the language was released
for public review.
Besides gaining the advantages of a hardware description language, the VHDL developers
sought to unify the designs of all the VHSIC contractors and subcontractors into a single
language. VHDL would allow anyone working on the program to define circuits and
models independently of design tools and independently, too, of technology or vendor of
the end product. Thus, a circuit could be designed and archived in VHDL, and later
fabricated with the most advanced technology.
In principle, functional parts of a design could be reused in different applications and
different technologies without repeating valuable design work. These benefits were
especially attractive to the DoD, which is often faced with obtaining equipment and spare
parts for decades from multiple suppliers through multiple generations of new
technologies. VHDL ultimately was included in Military Standard 454, and is a
requirement for all DoD projects.
In March of 1986, the IEEE took on the effort of standardizing VHDL. The VHDL Analysis
and Standardization Group (VASG) was set up to review the language, with the goal of
repairing known problems with the language and modifying the language where a broad
consensus formed around the modifications. The Air Force fully supported this work by
awarding a contract to Intermetrics to develop the support software for the new language
standard, now known as IEEE Std 1076.
VHDL has been compared to ADA and many of the goals are the same as for the ADA
language. VHDL evolution however has differed from ADA and as a result is establishing
itself as an industry standard language more rapidly. From the inception of the VHDL
program, the DoD acknowledged the weaknesses in the ADA standardization approach
and took steps which have resulted in a strong language. VHDL has benefited from
substantial industry review and participation throughout its development.
When in March 1986 all rights to the VHDL language were transferred to the IEEE, the
original version 7.2 language went through a phase of substantial changes driven primarily
by industry representation from CAE vendors as well as users. The goals of the IEEE in
developing a standard language were broader in scope. Driven by the need for a
production quality language suitable as a design tool to be used throughout the design
cycle, the IEEE enhanced the language substantially.
This effort resulted in the creation of a world-class hardware description language which
was ratified in December 1987 as the first industry standard hardware description
language with overwhelming support from industry. One important reason for the strong
support VHDL has received throughout industry is that unlike ADA, there are no other
standard languages which VHDL must compete against. Recently, however, the IEEE
standardization of the Verilog Hardware Description Language has started.

2.2 VHDL IEEE Std 1076-1993
Since its emergence as an IEEE standard, VHDL has been quite a success story. Despite the
fact that VHDL was created from scratch, more and more companies signal that they are
entering the VHDL marketplace or that they are expanding their current offerings. VHDL
has established itself as the premier hardware description language.
The IEEE is very determined that standards be used by their communities. Therefore, it
is an official IEEE requirement that all standards be reaffirmed at least every 5 years. This
reaffirmation may be anything from reaffirmation simpliciter to a radical change. The
important point is that a group of experts and users within the standard’s designated
community must care enough about the standard to keep it alive.
For VHDL, the 5 year reaffirmation IEEE requirement means that the language had to be
reballoted during 1992. Therefore, the VHDL Analysis and Standardization Group (VASG)
began planning the eventual reballoting in June of 1990.
The first decision made was to disallow radical changes to VHDL during this
restandardization period. The language had great forward momentum in the marketplace,
and radically altering it —even for sound technical reasons— could have a devastating
impact to that momentum. Second, for much the same reason, it was decided to make the
new version of VHDL as upward compatible as possible. Finally, it was decided to allow
change requests to come from the users.
In December 1992, the VHDL ballot successfully passed the IEEE requirements for the first
time. Then, the resolution process for the comments received during this first ballot started.
The team in charge to answer these comments changed the Language Reference Manual,
so there had to be a second ballot.

The second ballot was held in May 1993. The ballot results were positive: 155 affirmative,
40 negative and 14 abstention votes. This reflects a return rate of 85.6% and an approval
rate of 79%. The standard was then formally approved at the September 1993 meeting of
the IEEE Standards Board’s Review Committee.
The IEEE Std 1076-1993 was published during the first quarter of 1994. The new Language
Reference Manual (LRM) is self-sufficient, which means that the "old" LRM has become
obsolete. The new LRM includes an appendix identifying portability issues.
During the restandardization process, several working groups were formed. The following
working groups submitted a PAR (a PAR is a Project Authorization Request, which gives
a group a formal status as a working group moving towards a standard) to the IEEE New
Standards Committee, and were approved:
1076a Shared Variables - amendment to IEEE 1076-1993
1076.1 Analog Extensions to VHDL
1076.2 Standard Mathematical Package
1076.3 Standard Synthesis Package
1076.4 VHDL Timing and Back Annotation
1076.5 Utility Libraries
Recently (April 1994) a new DASC Test Study Group is being formed.
Another PAR which was approved, is the standardization of the Verilog HDL (PAR 1364).
As only the VHDL Hardware Description Language is within the scope of this report, we
did not include any further information on this PAR. However, we mention it for
completeness.
Section 2.3, titled Extensions of VHDL, gives information on PAR 1076a and PAR 1076.1.
Section 2.4, titled Definition of Standard Practices, gives information on PAR 1076.2, PAR
1076.3, PAR 1076.4, PAR 1076.5 and the Test Study Group. As the IEEE Standard
Multivalue Logic System for VHDL Model Interoperability (IEEE Std 1164-1993) and the
IEEE Waveform and Vector Exchange Specification (IEEE Std 1029.1-1991) also define
"Standard Practices", there are subsections giving information on this standard.
First, we have another subsection on VHDL ’93, highlighting some reflections on
VHDL ’93.

2.2.1 Reflections on VHDL ’93
The user requirements gathered during the restandardization process can be classified as
follows:
bugs and repairs (e.g., textio, which was ill-defined),
improvements (e.g., provide a no-change option for conditional signal assignments), and
new concepts (e.g., introduce analog modelling).
An additional division can be made between
requirements regarding the language itself and
requirements regarding its use (e.g., provide a SIN function).
Some of the requirements, mainly the synthesis-related ones, could be answered by the
standardization of ’standard’ packages, such as the std_logic_1164 package defining a
nine-state multi-value logic type and its associated resolution and logical functions (which
has already been voted on) or the standard packages of Ada. Such packages could be
written in pure VHDL and introduced as part of the standard or of sub-standards. An
example of a VHDL application that became a standard is WAVES.
Other requirements included changes in the definition of the language itself.
Among all the requests from users for a VHDL ’93 standardization, the requirements
concerning analog domain, and more precisely mixed-mode simulation, were most
numerous: about one fifth of the total. Europeans are particularly interested in this field.
In the very early stages of the standardization process, it became apparent that it would
not be possible, due to the very different levels of requests as well as to scheduling, for
analog extension to be included in VHDL ’93. However, because of the interest of
designers in this topic, a PAR (a Project Authorization Request) of VHDL has been
launched. The first draft of the Language Reference Manual is expected to be balloted by
the end of 1994.
Thus, VHDL ’93 (like VHDL ’87) does not cover the analog domain. Nevertheless, it is easy
to find many papers and even tutorials explaining how to model analog parts in VHDL
’87. For limited purposes, this has been done with VHDL ’87 and, of course, is possible
with VHDL ’93.
Indeed, VHDL ’93 offers some new possibilities for this purpose. The main one is the
introduction of a foreign "mechanism" that allows foreign models to be interfaced. These
models can potentially be described in an analog modelling language. This is not a "pure"
VHDL solution, and the interface is described so briefly that problems of portability and
dependency on tool vendors are inevitable. Nevertheless, this interface does exist, which
is an important advantage.
For people in search of a "pure" VHDL solution, one of the main problems is to identify
the "steady states" of the digital world during which the analog kernel may execute. Lastdelta
activation processes should solve this. It is also possible to imagine calling foreign
subprograms from these processes to activate an external analog kernel.
Analog modelling very often depends on parameters that can vary dynamically during
simulation. One example of this is temperature. The dynamic characteristics of such
parameters cannot be represented by the use of generic parameters. Their representation
as global signals or specific ports is definitely not satisfying. Shared variables, which are
in fact global variables, have been introduced into VHDL ’93 and could be used for this
purpose.

2.3 Extensions to VHDL
2.3.1 Analog VHDL (VHDL-A) Working Group
Name : Analog Extensions to VHDL WG (VHDL-A)
PAR : 1076.1
Chair : Jean-Michel Bergé
Contact list : see section 7.5
Information : see section 7.5 for details on how to get more information
Objectives
The purpose of the VHDL-A working group is to develop analog extensions to VHDL,
i.e. to enhance VHDL such that it can support the description and simulation of circuits
that exhibit continuous behaviour over time and over amplitude.
VHDL-A must be suitable for the description and simulation of digital, analog, and
mixed digital/analog systems. VHDL-A must be able to support any design
methodology and be technology independent.
Technology independence means that components of any technology (electrical,
mechanical, thermal, optical, fluid,...) must be supported, for example the attitude and
orbit of a satellite.
Mixed analog/digital simulations are a very important usage of VHDL-A, for example
mixed analog/digital simulation of an ASIC as well as mixed simulation of a mechanical
system (such as attitude and orbit of a satellite), together with a digital system (such as
the digital implementation of the satellite control system).
The analog part of VHDL-A should be targeted primarily towards the following
applications:
- DC and transient analysis,
- electronic circuits (OpAmps, PLLs, comparators,...),
- lumped element systems (meaning that microwaves cannot be handled).
The other domains (mechanical, thermal,...) could be easily introduced as they are
analogous to the electrical domain.
Using VHDL-A, it should be possible to describe the structural composition of analog
subcircuits connected by analog wires. Analog components could embody SPICE netlists
since the analog simulator should understand this de facto standard description.
Using VHDL-A, it should be possible to describe the behaviour of analog circuits. Two
styles should be provided: relations or equations, and procedural models. These two
styles will form the "core" of the analog part of VHDL-A.
Activities completed
The Design Objectives Document is completed and is available via anonymous ftp from
the VHDL-A repository mentioned in section 7.5.
Activities planned
Language design phase, documentation and validation phases are going on Goal: the LRM
(Language Reference Manual draft #1) will be ready for balloting by the end of 1994.
Responses from the first ballot should be received and ready for analysis by March 1995.
Further steps are to respond to all balloting responses, determine the result of the ballot,
modify documents as required, and resubmit for balloting. Most probably, there will be
at least two ballots. The earliest that balloting could be complete is August 1995. This
schedule is rather ambitious. As more information is gathered and work progresses, the
Work Group will reschedule the activities.
Relationship with other Working Group / Standards
Through DASC meetings.
It has been decided that VHDL-A will be an extension of the current VHDL and not a
supplement: i.e. the ballot only concerns analog extension (and not the entire language)
and the result (if positive) will consist in two standards. The previous STD 1076 remains
the same and the analog standard is created and refers to it.
2.3.2 Shared Variables Working Group
Name : Shared Variables WG (SVWG)
PAR : 1076a
Chair : Stephen Bailey
Contact list : see section 7.5
Information : see section 7.1 for details on how to get more information
Objectives
Shared Variables received the largest percentage of negative votes and/or comments in
balloting for VHDL 1076-1993. The working group was formed with the charter of
proposing an amendment to VHDL 1076-1993 (1076a) that would re-design the language
implementation of shared variables in order to address as many as possible of the concerns
that balloters of 1076-1993 have as possible.
Activities completed
The work is currently in the requirements phase. Requirements have been collected and
shortly the voting on each requirement’s relative importance will start (some requirements
are in conflict with others). The final requirements document was planned to be complete
by the end of February 1994.
A technical writer, LRM editor and technical review committees have been formed. A
requirements committee is completing the requirements work.
Activities planned
Once the relative importance of each requirement has been established, the technical
committee and writer will begin work on a language re-design proposal. Language
changes will be limited to areas related to shared variables.
The proposal will be submitted to the technical review committee and re-worked as
required by the committee’s feedback. Finally, the proposal will be submitted for a vote
of the voting membership of the SVWG. If approved, the proposal will be given to the
LRM editor who will integrate the changes with the LRM. The revised LRM will be
reviewed and then submitted to the IEEE for balloting.
Relationship with other Working Groups / Standards
Amendment to IEEE 1076-1993.
The OO-VHDL study group will be monitoring the shared variables progress since one
possible approach (monitors) is object-oriented.
2.4 Definition of Standard Practices
2.4.1 Mathematical Package Working Group
Name : VHDL Mathematical Package WG
PAR : 1076.2
Chair : Jose A. Torres
Contact list : see section 7.5
Information : see section 7.1 for details on how to get more information
Objectives
Develop a set of standard VHDL mathematical packages that include:
most often used real and complex elementary functions, and
the required data types and type conversion functions.
Activities completed
Strawman proposal for a math real and complex package is done (includes package
definition and body).
- Real functions include common real constants, common real functions and real
transcendental functions.
Work is in progress to put together a test bench.
- The NBS FORTRAN tests of math functions will be reused (15/10/93)
- The WG is checking with Mentor Graphics if the tests for their math package can be
used as a basis for the test bench (15/10/93).
- The Vantage test bench template can be used as a basis for the test bench (15/10/93).
- Some funding is available from Synopsys to develop a prototype of the test bench for
the math package (15/10/93).
Electronic form of the package is available on request.
Activities planned
Finish test bench,
Verify proposed functions,
Incorporate suggested changes, and
Ballot the package.
Currently, they are looking at June-July 1994 to start balloting the packages.
Relationship with other Working Groups / Standards
This standard is meant to be compliant with VHDL Standard 1076.
The VHDL Analog Extensions WG will submit analog requirements to the Math WG.
No requirements were received by 25/11/93.
The minutes of the 15/10/93 Math WG meeting mention the following: "There is still
the issue about the need for double precision functions and the possibility that a new
real type called FLOAT may be part of the VHDL-A effort. This type will require greater
accuracy than the current REAL type. The current proposed solution for this
requirement is to develop two math packages: one for each real type.
One consequence of such a decision is that we could ballot the REAL based math
package almost immediately and could ballot the FLOAT package at the same time that
analog is balloted."
The COMPLEX package is intended to support analog needs, complex numbers should
probably be based on FLOATS.